Embodiments of the present invention relate generally to a semiconductor device with active regions having a fin structure, and more specifically to a semiconductor device and a method of manufacturing the same not to generate a parasitic transistor while reducing a thickness of a wall oxide film formed at sidewalls of an active region.
As semiconductor devices have become more highly integrated, active regions has been scaled down. As a result, the channel length of transistors formed in the active region has been reduced.
If the channel length of transistors becomes smaller, the size of a channel region also becomes smaller, and short channel effects such as drain induced barrier lowering (DIBL) occur.
Thus, various methods for maximizing the performance of devices while reducing the size of elements formed over a substrate have been researched and developed. One of these various methods is a transistor having a fin structure.
The fin transistor is a transistor with a 3-dimensional channel structure that includes an active region having a protruded channel region, rather than a device isolation film, so that a gate may surround both side surfaces as well as the upper surface of the active region. Through this structure, the channel region is extended so that channels may be formed on three surfaces of the active region (upper surfaces and both side surfaces), thereby improving driving current characteristics.
In such fin structure, the width of the fin is increased in order to increase cell current. One of methods of increasing the width of the fin is to reduce a thickness of an insulating film (wall oxide film) buried in the lower portion of a device isolation film. That is, a space where the device isolation film is formed is determined by the width of the active region and the thickness of the wall oxide film formed over the active region. If the thickness of the wall oxide film is reduced while the space of the device isolation film is maintained, the width of the active region can be increased corresponding to the reduction, thereby increasing the width of the fin.
However, although the cell current is increased when the thickness of the wall oxide film is reduced, the wall oxide film protrudes above the device isolation film around the boundary of the device isolation film and the gate, and the protruded wall oxide film serves as a gate insulating film. In such a device, since the thickness of the wall oxide film is low, a parasitic transistor having a lower threshold voltage than that of the fin transistor is generated around the boundary of the device isolation film and the gate. As a result, the overall threshold voltage of the cell becomes lower.
Accordingly, it is desirable to establish a new method for reducing the thickness of the wall oxide film without generating a parasitic transistor.